This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-090951, filed Mar. 27, 2001 and No. 2002-064208, filed Mar. 8, 2002, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor chip mounting substrate (a wiring substrate) and a semiconductor device using the same. More specifically, the present invention relates to a pattern layout of a semiconductor chip mounting substrate having a conductive pad formed on a semiconductor chip mounting surface of an insulated substrate and a semiconductor device mounting a semiconductor chip on the substrate.
2. Description of the Related Art
Conventionally, the semiconductor chip mounting substrate used for mounting semiconductor chips is configured as follows, for example. Namely, there are formed a plurality of conductive pads and wirings respectively connected to these pads on one side of the insulated substrate, i.e., on the semiconductor chip mounting surface. Further, a plurality of wirings is also formed on the rear of the substrate. There is formed a plurality of through-hole conductors piercing both insulated substrate surfaces for electrically connecting corresponding wirings formed on both substrate surfaces.
A semiconductor chip is mounted on the semiconductor chip mounting surface of the semiconductor chip mounting substrate by means of die bonding. A bonding wire connects a conductive pad formed on the chip with a conductive pad on the semiconductor chip mounting surface. Further, insulating resin is used for sealing so as to cover the semiconductor chip mounting surface of the semiconductor chip mounting substrate including the semiconductor chip and bonding wires.
Conventionally, the semiconductor chip mounting substrate is specially developed and designed for mounting a specific type of semiconductor chip having a given chip size. Accordingly, such semiconductor chip mounting substrate prescribes the number of conductive pads and the placement state thereof formed on the chip mounting surface so as to properly meet the pad arrangement for the specific type of semiconductor chip.
In other words, the conventional semiconductor device needs to use special semiconductor chip mounting substrates according to different types of semiconductor chips.
When the type of mounted chips is changed or the chip size is reduced due to shrink, the semiconductor device using the conventional semiconductor chip mounting substrate necessitates the development and design of a new semiconductor chip mounting substrate.
As a result, the prior art not only remarkably degrades efficiency of the semiconductor device development, but also increases types of semiconductor chip mounting substrates. There occurs many wasteful production line changeovers and management works, increasing manufacturing costs.
According to a first aspect of the present invention, there is provided a wiring substrate comprises, an insulated substrate having a semiconductor chip mounting surface which provides a plurality of partially overlapping chip mounting areas capable of mounting a plurality of types of semiconductor chips with different chip sizes, and a plurality of conductive pads in a plurality of groups formed on the insulated substrate corresponding to semiconductor chips mountable on the plurality of chip mounting areas.
According to a second aspect of the present invention, there is provided a semiconductor device comprises, a wiring substrate having a semiconductor chip mounting surface which provides a plurality of partially overlapping chip mounting areas; a plurality of conductive pads in a plurality of groups formed on the wiring substrate corresponding to semiconductor chips mountable on the plurality of chip mounting areas, a semiconductor chip which is mounted on one of the plurality of chip mounting areas, the semiconductor chip having a plurality of conductive pads on the top surface, and a plurality of bonding wires to electrically connect the plurality of conductive pads provided on the top surface of the semiconductor chip with the plurality of conductive pads in a group corresponding to a semiconductor chip mounted on the chip mounting area.